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| SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Rev. 05 -- 2 October 2008 Product data sheet 1. General description The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission Control Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO Rdy register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows on-board diagnostics. The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5 bits, 6 bits, 7 bits, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and has software flow control and hardware flow control capabilities. The SC16C752B is available in plastic LQFP48 and HVQFN32 packages. 2. Features I I I I I I Pin compatible with SC16C2550 with additional enhancements Up to 5 Mbit/s baud rate (at 3.3 V and 5 V; at 2.5 V maximum baud rate is 3 Mbit/s) 64-byte transmit FIFO 64-byte receive FIFO with error flags Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt generation Software/hardware flow control N Programmable Xon/Xoff characters N Programmable auto-RTS and auto-CTS Optional data flow resume by Xon any character DMA signalling capability for both received and transmitted data Supports 5 V, 3.3 V and 2.5 V operation I I I NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs I I I I I I I I I I I I I I 5 V tolerant on input only pins1 Software selectable baud rate generator Prescaler provides additional divide-by-4 function Industrial temperature range (-40 C to +85 C) Pin and software compatible with SC16C752, TL16C752 Fast data bus access time Programmable Sleep mode Programmable serial interface characteristics N 5-bit, 6-bit, 7-bit, or 8-bit characters N Even, odd, or no parity bit generation and detection N 1, 1.5, or 2 stop bit generation False start bit detection Complete status reporting capabilities in both normal and Sleep mode Line break generation and detection Internal test and loopback capabilities Fully prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, and CD) 3. Ordering information Table 1. Ordering information Package Name SC16C752BIB48 SC16C752BIBS LQFP48 HVQFN32 Description plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm Version SOT313-2 SOT617-1 Type number 1. For data bus, D7 to D0, see Table 24 "Limiting values". (c) NXP B.V. 2008. All rights reserved. SC16C752B_5 Product data sheet Rev. 05 -- 2 October 2008 2 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 4. Block diagram SC16C752B TRANSMIT FIFO REGISTERS DATA BUS AND CONTROL LOGIC FLOW CONTROL LOGIC TRANSMIT SHIFT REGISTER TXA, TXB D0 to D7 IOR IOW RESET INTERCONNECT BUS LINES AND CONTROL SIGNALS RECEIVE FIFO REGISTERS RECEIVE SHIFT REGISTER RXA, RXB A0 to A2 CSA CSB REGISTER SELECT LOGIC FLOW CONTROL LOGIC DTRA, DTRB RTSA, RTSB OPA, OPB MODEM CONTROL LOGIC INTA, INTB TXRDYA, TXRDYB RXRDYA, RXRDYB INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR CTSA, CTSB RIA, RIB CDA, CDB DSRA, DSRB 002aaa600 XTAL1 XTAL2 Fig 1. Block diagram SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 3 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 5. Pinning information 5.1 Pinning 43 TXRDYA 39 DSRA 38 CTSA 40 CDA 42 VCC 41 RIA D5 D6 D7 RXB RXA TXRDYB TXA TXB OPB 1 2 3 4 5 6 7 8 9 37 n.c. 36 RESET 35 DTRB 34 DTRA 33 RTSA 32 OPA 31 RXRDYA 30 INTA 29 INTB 28 A0 27 A1 26 A2 25 n.c. n.c. 24 002aaa601 002aaa950 46 D2 IOW 15 48 D4 47 D3 45 D1 CDB 16 SC16C752BIB48 CSA 10 CSB 11 n.c. 12 XTAL1 13 XTAL2 14 GND 17 RXRDYB 18 IOR 19 DSRB 20 RIB 21 RTSB 22 25 CTSA CTSB 16 CTSB 23 Fig 2. Pin configuration for LQFP48 44 D0 32 D5 31 D4 30 D3 29 D2 28 D1 D6 D7 RXB RXA TXA TXB OPB CSA 1 2 3 4 5 6 7 8 XTAL1 10 XTAL2 11 IOW 12 GND 13 IOR 14 RTSB 15 9 27 D0 terminal 1 index area 26 VCC 24 RESET 23 RTSA 22 OPA 21 INTA 20 INTB 19 A0 18 A1 17 A2 SC16C752BIBS CSB Transparent top view Fig 3. Pin configuration for HVQFN32 SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 4 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 5.2 Pin description Table 2. Symbol A0 A1 A2 CDA CDB Pin description Pin LQFP48 HVQFN32 28 27 26 40 16 19 18 17 I I I I i Address 0 select bit. Internal registers address selection. Address 1 select bit. Internal registers address selection. Address 2 select bit. Internal registers address selection. Carrier Detect (active LOW). These inputs are associated with individual UART channels A and B. A logic LOW on these pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reflected in the Modem Status Register (MSR). Chip Select (active LOW). These pins enable data transfers between the user CPU and the SC16C752B for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a logic LOW on the respective CSA and CSB pins. Clear to Send (active LOW). These inputs are associated with individual UART channels A and B. A logic 0 (LOW) on the CTS pins indicates the modem or data set is ready to accept transmit data from the SC16C752B. Status can be tested by reading MSR[4]. These pins only affect the transmit and receive operations when auto-CTS function is enabled via the Enhanced Feature Register EFR[7] for hardware flow control operation. Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Type Description CSA CSB 10 11 8 9 I I CTSA CTSB 38 23 25 16 I I D0 D1 D2 D3 D4 D5 D6 D7 DSRA DSRB 44 45 46 47 48 1 2 3 39 20 27 28 29 30 31 32 1 2 - I/O I/O I/O I/O I/O I/O I/O I/O I I Data Set Ready (active LOW). These inputs are associated with individual UART channels A and B. A logic 0 (LOW) on these pins indicates the modem or data set is powered-on and is ready for data exchange with the UART. The state of these inputs is reflected in the Modem Status Register (MSR). Data Terminal Ready (active LOW). These outputs are associated with individual UART channels A and B. A logic 0 (LOW) on these pins indicates that the SC16C752B is powered-on and ready. These pins can be controlled via the modem control register. Writing a logic 1 to MCR[0] will set the DTR output to logic 0 (LOW), enabling the modem. The output of these pins will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. Signal and power ground Interrupt A and B (active HIGH). These pins provide individual channel interrupts INTA and INTB. INTA and INTB are enabled when MCR[3] is set to a logic 1, interrupt sources are enabled in the Interrupt Enable Register (IER). Interrupt conditions include: receiver errors, available receiver buffer data, available transmit buffer space, or when a modem status flag is detected. INTA, INTB are in the high-impedance state after reset. Input/Output Read strobe (active LOW). A HIGH-to-LOW transition on IOR will load the contents of an internal register defined by address bits A0 to A2 onto the SC16C752B data bus (D0 to D7) for access by external CPU. (c) NXP B.V. 2008. All rights reserved. DTRA DTRB 34 35 - O O GND INTA INTB 17 30 29 13 21 20 I O O IOR 19 14 I SC16C752B_5 Product data sheet Rev. 05 -- 2 October 2008 5 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Table 2. Symbol IOW Pin description ...continued Pin LQFP48 HVQFN32 15 12 I Input/Output Write strobe (active LOW). A LOW-to-HIGH transition on IOW will transfer the contents of the data bus (D0 to D7) from the external CPU to an internal register that is defined by address bits A0 to A2 and CSA and CSB. not connected User defined outputs. This function is associated with individual channels A and B. The state of these pins is defined by the user through the software settings of MCR[3]. INTA-INTB are set to active mode and OPA-OPB to a logic 0 when MCR[3] is set to a logic 1. INTA-INTB are set to the 3-state mode and OPA-OPB to a logic 1 when MCR[3] is set to a logic 0. The output of these two pins is HIGH after reset. Reset. This pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. RESET is an active HIGH input. Ring Indicator (active LOW). These inputs are associated with individual UART channels, A and B. A logic 0 on these pins indicates the modem has received a ringing signal from the telephone line. A LOW-to-HIGH transition on these input pins generates a modem status interrupt, if enabled. The state of these inputs is reflected in the Modem Status Register (MSR). Request to Send (active LOW). These outputs are associated with individual UART channels, A and B. A logic 0 on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this pin to a logic 0, indicating data is available. After a reset these pins are set to a logic 1. These pins only affect the transmit and receive operations when auto-RTS function is enabled via the Enhanced Feature Register (EFR[6]) for hardware flow control operation. Receive data input. These inputs are associated with individual serial channel data to the SC16C752B. During the local Loopback mode, these RX input pins are disabled and TX data is connected to the UART RX input internally. Receive Ready (active LOW). RXRDYA or RXRDYB goes LOW when the trigger level has been reached or the FIFO has at least one character. It goes HIGH when the RX FIFO is empty. Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC16C752B. During the local Loopback mode, the TX output pin is disabled and TX data is internally connected to the UART RX input. Transmit Ready (active LOW). TXRDYA or TXRDYB go LOW when there are at least a trigger level number of spaces available or when the FIFO is empty. It goes HIGH when the FIFO is full or not empty. Power supply input Crystal or external clock input. Functions as a crystal input or as an external clock input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see Figure 13). Alternatively, an external clock can be connected to this pin to provide custom data rates. Output of the crystal oscillator or buffered clock. (See also XTAL1.) XTAL2 is used as a crystal oscillator output or a buffered clock output. Type Description n.c. OPA OPB 12, 24, 25, 37 32 9 22 7 O O RESET 36 24 I RIA RIB 41 21 - I I RTSA RTSB 33 22 23 15 O O RXA RXB RXRDYA RXRDYB TXA TXB TXRDYA TXRDYB VCC XTAL1 5 4 31 18 7 8 43 6 42 13 4 3 5 6 26 10 I I O O O O O O I I XTAL2 14 11 O SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 6 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6. Functional description The SC16C752B UART is pin-compatible with the SC16C2550 UART. It provides more enhanced features. All additional features are provided through a special Enhanced Feature Register (EFR). The UART will perform serial-to-parallel conversion on data characters received from peripheral devices or modems, and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each channel of the SC16C752B UART can be read at any time during functional operation by the processor. The SC16C752B can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow signalling of DMA transfers. The SC16C752B has selectable hardware flow control and software flow control. Hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the RTS output and CTS input signals. Software flow control automatically controls data flow by using programmable Xon/Xoff characters. The UART includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (216 - 1). 6.1 Trigger levels The SC16C752B provides independent selectable and programmable trigger levels for both receiver and transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of one byte. The selectable trigger levels are available via the FIFO Control Register (FCR). The programmable trigger levels are available via the Trigger Level Register (TLR). 6.2 Hardware flow control Hardware flow control is comprised of auto-CTS and auto-RTS. Auto-CTS and auto-RTS can be enabled/disabled independently by programming EFR[7:6]. With auto-CTS, CTS must be active before the UART can transmit data. Auto-RTS only activates the RTS output when there is enough room in the FIFO to receive data and de-activates the RTS output when the RX FIFO is sufficiently full. The halt and resume trigger levels in the TCR determine the levels at which RTS is activated/deactivated. If both auto-CTS and auto-RTS are enabled, when RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has empty space. Thus, overrun errors are eliminated during hardware flow control. If not enabled, overrun errors occur if the transmit data rate exceeds the receive FIFO servicing latency. SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 7 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs UART 1 SERIAL TO PARALLEL RX FIFO FLOW CONTROL D7 to D0 PARALLEL TO SERIAL TX FIFO FLOW CONTROL CTS RTS TX RX RTS CTS UART 2 PARALLEL TO SERIAL TX FIFO FLOW CONTROL D7 to D0 SERIAL TO PARALLEL RX FIFO FLOW CONTROL 002aaa228 RX TX Fig 4. Autoflow control (auto-RTS and auto-CTS) example 6.2.1 Auto-RTS Auto-RTS data flow control originates in the receiver block (see Figure 1 "Block diagram" on page 3). Figure 5 shows RTS functional timing. The receiver FIFO trigger levels used in auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is de-asserted. The sending device (e.g., another UART) may send an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it may not recognize the de-assertion of RTS until it has begun sending the additional byte. RTS is automatically reasserted once the receiver FIFO reaches the resume trigger level programmed via TCR[7:4]. This re-assertion allows the sending device to resume transmission. RX Start byte N Stop Start byte N + 1 Stop Start RTS IOR 1 2 N N+1 002aaa226 N = receiver FIFO trigger level. The two blocks in dashed lines cover the case where an additional byte is sent, as described in Section 6.2.1. Fig 5. RTS functional timing SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 8 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.2.2 Auto-CTS The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS must be de-asserted before the middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host system. When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error may result. TX Start byte 0 to 7 Stop Start byte 0 to 7 Stop CTS 002aaa227 When CTS is LOW, the transmitter keeps sending serial data out. When CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte, but is does not send the next byte. When CTS goes from HIGH to LOW, the transmitter begins sending data again. Fig 6. CTS functional timing 6.3 Software flow control Software flow control is enabled through the enhanced feature register and the modem control register. Different combinations of software flow control can be enabled by setting different combinations of EFR[3:0]. Table 3 shows software flow control options. Table 3. EFR[3] 0 1 0 1 X X X 1 0 1 Software flow control options (EFR[0:3]) EFR[2] 0 0 1 1 X X X 0 1 1 EFR[1] X X X X 0 1 0 1 1 1 EFR[0] X X X X 0 0 1 1 1 1 TX, RX software flow controls no transmit flow control transmit Xon1, Xoff1 transmit Xon2, Xoff2 transmit Xon1, Xon2, Xoff1, Xoff2 no receive flow control receiver compared Xon1, Xoff1 receiver compares Xon2, Xoff2 transmit Xon1, Xoff1 receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit Xon2, Xoff2 receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit Xon1, Xon2, Xoff1, Xoff2 receiver compares Xon1 and Xon2, Xoff1 and Xoff2 SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 9 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs There are two other enhanced features relating to software flow control: * Xon Any function (MCR[5]): Operation will resume after receiving any character after recognizing the Xoff character. It is possible that an Xon1 character is recognized as an Xon Any character, which could cause an Xon2 character to be written to the RX FIFO. * Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the RX FIFO. 6.3.1 RX When software flow control operation is enabled, the SC16C752B will compare incoming data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be received sequentially). When the correct Xoff character are received, transmission is halted after completing transmission of the current character. Xoff detection also sets IIR[4] (if enabled via IER[5]) and causes INT to go HIGH. To resume transmission, an Xon1/Xon2 character must be received (in certain cases Xon1 and Xon2 must be received sequentially). When the correct Xon characters are received, IIR[4] is cleared, and the Xoff interrupt disappears. 6.3.2 TX Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the halt trigger level programmed in TCR[3:0]. Xon1/Xon2 character is transmitted when the RX FIFO reaches the resume trigger level programmed in TCR[7:4]. The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an ordinary byte from the FIFO. This means that even if the word length is set to be 5, 6, or 7 characters, then the 5, 6, or 7 least significant bits of Xoff1/Xoff2, Xon1/Xoff2 will be transmitted. (Note that the transmission of 5 bits, 6 bits, or 7 bits of a character is seldom done, but this functionality is included to maintain compatibility with earlier designs.) It is assumed that software flow control and hardware flow control will never be enabled simultaneously. Figure 7 shows an example of software flow control. SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 10 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.3.3 Software flow control example UART1 UART2 TRANSMIT FIFO RECEIVE FIFO PARALLEL-TO-SERIAL data SERIAL-TO-PARALLEL Xoff-Xon-Xoff SERIAL-TO-PARALLEL PARALLEL-TO-SERIAL Xon1 WORD Xon1 WORD Xon2 WORD Xon2 WORD Xoff1 WORD Xoff1 WORD Xoff2 WORD compare programmed Xon-Xoff characters Xoff2 WORD 002aaa229 Fig 7. Software flow control example 6.3.3.1 Assumptions UART1 is transmitting a large text file to UART2. Both UARTs are using software flow control with single character Xoff (0Fh) and Xon (0Dh) tokens. Both have Xoff threshold (TCR[3:0] = Fh) set to 60, and Xon threshold (TCR[7:4] = 8h) set to 32. Both have the interrupt receive threshold (TLR[7:4] = Dh) set to 52. UART 1 begins transmission and sends 52 characters, at which point UART2 will generate an interrupt to its processor to service the RCV FIFO, but assume the interrupt latency is fairly long. UART1 will continue sending characters until a total of 60 characters have been sent. At this time, UART2 will transmit a 0Fh to UART1, informing UART1 to halt transmission. UART1 will likely send the 61st character while UART2 is sending the Xoff character. Now UART2 is serviced and the processor reads enough data out of the RX FIFO that the level drops to 32. UART2 will now send a 0Dh to UART1, informing UART1 to resume transmission. SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 11 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.4 Reset Table 4 summarizes the state of register after reset. Table 4. Register Interrupt Enable Register Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register Enhanced Feature Register Receiver Holding Register Transmitter Holding Register Transmission Control Register Trigger Level Register [1] Register reset functions[1] Reset control RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET Reset state all bits cleared bit 0 is set; all other bits cleared all bits cleared reset to 0001 1101 (1Dh) all bits cleared bit 5 and bit 6 set; all other bits cleared bits [3:0] cleared; bits [7:4] input signals all bits cleared pointer logic cleared pointer logic cleared all bits cleared all bits cleared Registers DLL, DLM, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the top-level reset signal RESET, i.e., they hold their initialization values during reset. Table 5 summarizes the state of registers after reset. Table 5. Signal TX RTS DTR RXRDY TXRDY Signal RESET functions Reset control RESET RESET RESET RESET RESET Reset state HIGH HIGH HIGH HIGH LOW SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 12 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.5 Interrupts The SC16C752B has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of interrupts and the INT signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bit 0 to bit 3 and bit 5 to bit 7. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5:0]. Table 6 summarizes the interrupt control functions. Table 6. IIR[5:0] 00 0001 00 0110 Interrupt control functions Priority level None 1 Interrupt type none receiver line status Interrupt source none OE, FE, PE, or BI errors occur in characters in the RX FIFO Interrupt reset method none FE, PE, BI: all erroneous characters are read from the RX FIFO. OE: read LSR 00 1100 00 0100 2 2 RX time-out RHR interrupt stale data in RX FIFO DRDY (data ready) (FIFO disable) RX FIFO above trigger level (FIFO enable) 00 0010 3 THR interrupt TFE (THR empty) (FIFO disable) TX FIFO passes above trigger level (FIFO enable) 00 0000 01 0000 10 0000 4 5 6 modem status Xoff interrupt CTS, RTS MSR[3:0] = logic 0 receive Xoff character(s)/special character read MSR receive Xon character(s)/Read of IIR read IIR or a write to the THR read RHR read RHR RTS pin or CTS pin change state from read IIR active (LOW) to inactive (HIGH) It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always represent the error status for the received character at the top of the RX FIFO. Reading the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros. For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read of the LSR. SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 13 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.5.1 Interrupt mode operation In interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of the receiver and transmitter by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced. Figure 8 shows interrupt mode operation. IOW / IOR INT PROCESSOR IIR IER 1 1 1 1 THR RHR 002aaa230 Fig 8. Interrupt mode operation 6.5.2 Polled mode operation In polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be checked by polling the Line Status Register (LSR). This mode is an alternative to the FIFO interrupt mode of operation where the status of the receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 9 shows FIFO polled mode operation. IOW / IOR PROCESSOR LSR IER 0 0 0 0 THR RHR 002aaa231 Fig 9. FIFO polled mode operation SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 14 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.6 DMA operation There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by FCR[3]. In DMA mode 0 or FIFO disable (FCR[0] = 0) DMA occurs in single character transfers. In DMA mode 1, multi-character (or block) DMA transfers are managed to relieve the processor for longer periods of time. 6.6.1 Single DMA transfers (DMA mode 0/FIFO disable) Figure 10 shows TXRDY and RXRDY in DMA mode 0/FIFO disable. TX RX TXRDY RXRDY wrptr at least one location filled rdptr at least one location filled TXRDY RXRDY wrptr FIFO EMPTY rdptr FIFO EMPTY 002aaa232 Fig 10. TXRDY and RXRDY in DMA mode 0/FIFO disable 6.6.1.1 Transmitter When empty, the TXRDY signal becomes active. TXRDY will go inactive after one character has been loaded into it. 6.6.1.2 Receiver RXRDY is active when there is at least one character in the FIFO. It becomes inactive when the receiver is empty. SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 15 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.6.2 Block DMA transfers (DMA mode 1) Figure 11 shows TXRDY and RXRDY in DMA mode 1. wrptr TX trigger level TXRDY rdptr RX RXRDY at least one location filled FIFO full trigger level wrptr TXRDY RXRDY rdptr FIFO EMPTY 002aaa234 Fig 11. TXRDY and RXRDY in DMA mode 1 6.6.2.1 Transmitter TXRDY is active when there is a trigger level number of spaces available. It becomes inactive when the FIFO is full. 6.6.2.2 Receiver RXRDY becomes active when the trigger level has been reached, or when a time-out interrupt occurs. It will go inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR[7]. 6.7 Sleep mode Sleep mode is an enhanced feature of the SC16C752B UART. It is enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when: * The serial data input line, RX, is idle (see Section 6.8 "Break and time-out conditions"). * The TX FIFO and TX shift register are empty. * There are no interrupts pending except THR and time-out interrupts. Remark: Sleep mode will not be entered if there is data in the RX FIFO. In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are clocked using these clocks, the power consumption is greatly reduced. The UART will wake up when any change is detected on the RX line, when there is any change in the state of the modem input pins, or if data is written to the TX FIFO. Remark: Writing to the divisor latches DLL and DLM to set the baud clock must not be done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4] before writing to DLL or DLM. SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 16 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.8 Break and time-out conditions An RX idle condition is detected when the receiver line, RX, has been HIGH for 4 character time. The receiver line is sampled midway through each bit. When a break condition occurs, the TX line is pulled LOW. A break condition is activated by setting LCR[6]. 6.9 Programmable baud rate generator The SC16C752B UART contains a programmable baud generator that takes any clock input and divides it by a divisor in the range between 1 and (216 - 1). An additional divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in Figure 12. The output frequency of the baud rate generator is 16 x the baud rate. The formula for the divisor is given in Equation 1: XTAL1 crystal input frequency ------------------------------------------------------------------------------------ - prescaler divisor = ----------------------------------------------------------------------------------------( desired baud rate x 16 ) Where: prescaler = 1, when MCR[7] is set to logic 0 after reset (divide-by-1 clock selected); prescaler = 4, when MCR[7] is set to logic 1 after reset (divide-by-4 clock selected). Remark: The default value of prescaler after reset is divide-by-1. Figure 12 shows the internal prescaler and baud rate generator circuitry. (1) PRESCALER LOGIC (DIVIDE-BY-1) XTAL1 XTAL2 INTERNAL OSCILLATOR LOGIC MCR[7] = 0 internal baud rate clock for transmitter and receiver input clock reference clock MCR[7] = 1 BAUD RATE GENERATOR LOGIC PRESCALER LOGIC (DIVIDE-BY-4) 002aaa233 Fig 12. Prescaler and baud rate generator block diagram DLL and DLM must be written to in order to program the baud rate. DLL and DLM are the least significant and most significant byte of the baud rate divisor. If DLL and DLM are both zero, the UART is effectively disabled, as no baud clock will be generated. Remark: The programmable baud rate generator is provided to select both the transmit and receive clock rates. Table 7 and Table 8 show the baud rate and divisor correlation for crystal with frequency 1.8432 MHz and 3.072 MHz, respectively. Figure 13 shows the crystal clock circuit reference. SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 17 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Baud rates using a 1.8432 MHz crystal Divisor used to generate 16x clock 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 Baud rates using a 3.072 MHz crystal Divisor used to generate 16x clock 2304 2560 1745 1428 1280 640 320 160 107 96 80 53 40 27 20 10 5 1.23 0.628 0.312 0.026 0.034 Percent error difference between desired and actual 2.86 0.69 0.026 0.058 Percent error difference between desired and actual Table 7. Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 Table 8. Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 18 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs XTAL1 XTAL2 XTAL1 XTAL2 1.5 k X1 1.8432 MHz X1 1.8432 MHz C1 22 pF C2 33 pF C1 22 pF C2 47 pF 002aaa870 Fig 13. Crystal oscillator connections 7. Register descriptions Each register is selected using address lines A0, A1, A2, and in some cases, bits from other registers. The programming combinations for register selection are shown in Table 9. Table 9. A2 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 [1] [2] [3] [4] [5] [6] SC16C752B_5 Register map - read/write properties A0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 Read mode Receive Holding Register (RHR) Interrupt Enable Register (IER) Interrupt Identification Register (IIR) Line Control Register (LCR) Modem Control Register (MCR)[1] Line Status Register (LSR) Modem Status Register (MSR) Scratchpad Register (SPR) Divisor Latch LSB (DLL)[2][3] Divisor Latch MSB (DLM)[2][3] Enhanced Feature Register (EFR)[2][4] Xon1 word[2][4] Xon2 word[2][4] Xoff1 word[2][4] Xoff2 word[2][4] Transmission Control Register FIFO ready register[2][6] (TCR)[2][5] Trigger Level Register (TLR)[2][5] Scratchpad Register Divisor Latch LSB[2][3] Divisor Latch MSB[2][3] Enhanced Feature Register[2][4] Xon1 word[2][4] Xon2 word[2][4] Xoff1 word[2][4] Xoff2 word[2][4] Transmission Control Register[2][5] Trigger Level Register[2][5] Write mode Transmit Holding Register (THR) Interrupt Enable Register FIFO Control Register (FCR) Line Control Register Modem Control Register[1] A1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 1 1 1 MCR[7] can only be modified when EFR[4] is set. Accessed by a combination of address pins and register bits. Accessible only when LCR[7] is logic 1. Accessible only when LCR is set to 1011 1111 (BFh). Accessible only when EFR[4] = logic 1 and MCR[6] = logic 1, i.e., EFR[4] and MCR[6] are read/write enables. Accessible only when CSA or CSB = logic 0, MCR[2] = logic 1, and loopback is disabled (MCR[4] = logic 0). (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 19 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Table 10 lists and describes the SC16C752B internal registers. Table 10. SC16C752B internal registers Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/ Write R W R/W A2 A1 A0 Register Bit 7 General register set[1] 0 0 0 0 0 0 0 0 1 RHR THR IER bit 7 bit 7 0/CTS interrupt enable[2] RX trigger level (MSB) FCR[0] bit 6 bit 6 0/RTS interrupt enable[2] RX trigger level (LSB) bit 5 bit 5 0/Xoff[2] bit 4 bit 4 bit 3 bit 3 bit 2 bit 2 bit 1 bit 1 bit 0 bit 0 Rx data available interrupt FIFO enable 0/X sleep modem receive THR mode[2] status line status empty interrupt interrupt interrupt 0/TX trigger level (LSB)[2] 0/Xoff DMA mode select TX FIFO reset RX FIFO reset 0 1 0 FCR 0/TX trigger level (MSB)[2] 0/CTS, RTS W 0 1 0 IIR FCR[0] interrupt interrupt priority priority bit 2 bit 1 parity enable IRQ enable OP framing error CD bit 3 bit 3 bit 3 0 interrupt priority bit 0 interrupt status word length bit 0 DTR R 0 1 1 LCR DLAB break control bit TCR and TLR enable[2] set parity parity type select 0/Xon Any[2] 0/enable loopback break interrupt CTS bit 4 bit 4 bit 4 RX FIFO A status bit 4 bit 12 number of word stop bits length bit 1 FIFO ready enable parity error RI bit 2 bit 2 bit 2 0 RTS R/W 1 0 0 MCR 1x or 1x / 4 clock[2] 0/error in RX FIFO CD bit 7 bit 7 bit 7 0 R/W 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 0 1 1 LSR MSR SPR TCR TLR FIFO Rdy DLL DLM EFR THR and THR TSR empty empty RI bit 6 bit 6 bit 6 0 DSR bit 5 bit 5 bit 5 RX FIFO B status bit 5 bit 13 overrun error DSR bit 1 bit 1 bit 1 TX FIFO B status bit 1 bit 9 software flow control bit 1 bit 1 bit 1 bit 1 bit 1 data in receiver CTS bit 0 bit 0 bit 0 TX FIFO A status bit 0 bit 8 software flow control bit 0 bit 0 bit 0 bit 0 bit 0 R R R/W R/W R/W R Special register set[3] 0 0 0 0 0 1 0 1 0 bit 7 bit 15 set[4] auto CTS auto RTS Special Enable character IER[7:4], detect FCR[5:4], MCR[7:5] bit 5 bit 5 bit 5 bit 5 bit 4 bit 4 bit 4 bit 4 software flow control bit 3 bit 3 bit 3 bit 3 bit 3 software flow control bit 2 bit 2 bit 2 bit 2 bit 2 R/W bit 6 bit 14 bit 3 bit 11 bit 2 bit 10 R/W R/W Enhanced register 1 1 1 1 [1] [2] [3] [4] 0 0 1 1 0 1 0 1 Xon1 Xon2 Xoff1 Xoff2 bit 7 bit 7 bit 7 bit 7 bit 6 bit 6 bit 6 bit 6 R/W R/W R/W R/W These registers are accessible only when LCR[7] = logic 0. These bits can only be modified if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled. The Special register set is accessible only when LCR[7] is set to a logic 1. Enhanced Feature Register; Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to BFh. (c) NXP B.V. 2008. All rights reserved. SC16C752B_5 Product data sheet Rev. 05 -- 2 October 2008 20 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Remark: Refer to the notes under Table 9 for more register access information. 7.1 Receiver Holding Register (RHR) The receiver section consists of the Receiver Holding Register (RHR) and the Receiver Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX terminal. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the Line Control Register. If the FIFO is disabled, location zero of the FIFO is used to store the characters. Remark: In this case, characters are overwritten if overflow occurs. If overflow occurs, characters are lost. The RHR also stores the error status bits associated with each character. 7.2 Transmit Holding Register (THR) The transmitter section consists of the Transmit Holding Register (THR) and the Transmit Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and shifts it into the TSR, where it is converted to serial data and moved out on the TX terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are lost if overflow occurs. SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 21 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.3 FIFO Control Register (FCR) This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and receiver trigger levels, and selecting the type of DMA signalling. Table 11 shows FIFO control register bit settings. Table 11. Bit 7:6 FIFO Control Register bits description Description RCVR trigger. Sets the trigger level for the RX FIFO. 00 - 8 characters 01 - 16 characters 10 - 56 characters 11 - 60 characters 5:4 FCR[5] (MSB), FCR[4] (LSB) TX trigger. Sets the trigger level for the TX FIFO. 00 - 8 spaces 01 - 16 spaces 10 - 32 spaces 11 - 56 spaces FCR[5:4] can only be modified and enabled when EFR[4] is set. This is because the transmit trigger level is regarded as an enhanced function. 3 FCR[3] DMA mode select. logic 0 = set DMA mode `0' logic 1 = set DMA mode `1' 2 FCR[2] Reset TX FIFO. logic 0 = no FIFO transmit reset (normal default condition) logic 1 = Clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. 1 FCR[1] Reset RX FIFO. logic 0 = no FIFO receive reset (normal default condition) logic 1 = Clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. 0 FCR[0] FIFO enable. logic 0 = disable the transmit and receive FIFO (normal default condition) logic 1 = enable the transmit and receive FIFO. Symbol FCR[7] (MSB), FCR[6] (LSB) SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 22 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.4 Line Control Register (LCR) This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. Table 12 shows the Line Control Register bit settings. Table 12. Bit 7 Line Control Register bits description Description Divisor latch enable. logic 0 = divisor latch disabled (normal default condition) logic 1 = divisor latch enabled 6 LCR[6] Break control bit. When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR[6] to a logic 0. logic 0 = no TX break condition (normal default condition) logic 1 = forces the transmitter output (TX) to a logic 0 to alert the communication terminal to a line break condition 5 LCR[5] Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1). logic 0 = parity is not forced (normal default condition) LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logic 1 for the transmit and receive data. LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logic 0 for the transmit and receive data. 4 LCR[4] Parity type select. logic 0 = odd parity is generated (if LCR[3] = 1) logic 1 = even parity is generated (if LCR[3] = 1) 3 LCR[3] Parity enable. logic 0 = no parity (normal default condition) logic 1 = a parity bit is generated during transmission and the receiver checks for received parity 2 LCR[2] Number of Stop bits. Specifies the number of stop bits. 0 - 1 stop bit (word length = 5, 6, 7, 8) 1 - 1.5 stop bits (word length = 5) 1 - 2 stop bits (word length = 6, 7, 8) 1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received. 00 - 5 bits 01 - 6 bits 10 - 7 bits 11 - 8 bits Symbol LCR[7] SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 23 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.5 Line Status Register (LSR) Table 13 shows the Line Status Register bit settings. Table 13. Bit 7 Line Status Register bits description Description FIFO data error. logic 0 = no error (normal default condition) logic 1 = At least one parity error, framing error, or break indication is in the receiver FIFO. This bit is cleared when no more errors are present in the FIFO. 6 LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator. logic 0 = transmitter hold and shift registers are not empty logic 1 = transmitter hold and shift registers are empty 5 LSR[5] THR empty. This bit is the Transmit Holding Register Empty indicator. logic 0 = Transmit Holding Register is not empty logic 1 = Transmit Holding Register is empty. The processor can now load up to 64 bytes of data into the THR if the TX FIFO is enabled. 4 LSR[4] Break interrupt. logic 0 = No break condition (normal default condition) logic 1 = A break condition occurred and associated byte is 00, i.e., RX was LOW for one character time frame 3 LSR[3] Framing error. logic 0 = no framing error in data being read from RX FIFO (normal default condition) logic 1 = framing error occurred in data being read from RX FIFO, i.e., received data did not have a valid stop bit. 2 LSR[2] Parity error. logic 0 = no parity error (normal default condition) logic 1 = parity error in data being read from RX FIFO 1 LSR[1] Overrun error. logic 0 = no overrun error (normal default condition) logic 1 = overrun error has occurred 0 LSR[0] Data in receiver. logic 0 = no data in receive FIFO (normal default condition) logic 1 = at least one character in the RX FIFO Symbol LSR[7] When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX FIFO (next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the RX FIFO is output directly onto the output data bus, DI[4:2], when the LSR is read. Therefore, errors in a character are identified by reading the LSR and then reading the RHR. LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when there are no more errors remaining in the FIFO. Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO read pointer is incremented by reading the RHR. SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 24 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.6 Modem Control Register (MCR) The MCR controls the interface with the mode, data set, or peripheral device that is emulating the modem. Table 14 shows modem control register bit settings. Table 14. Bit 7 Modem Control Register bits description Description Clock select. logic 0 = divide-by-1 clock input logic 1 = divide-by-4 clock input 6 MCR[6][1] TCR and TLR enable. logic 0 = no action logic 1 = enable access to the TCR and TLR registers 5 MCR[5][1] Xon Any. logic 0 = disable Xon Any function logic 1 = enable Xon Any function 4 MCR[4] Enable loopback. logic 0 = normal operating mode. logic 1 = enable local Loopback mode (internal). In this mode the MCR[3:0] signals are looped back into MSR[7:4] and the TX output is looped back to the RX input internally. 3 MCR[3] IRQ enable OP. logic 0 = forces INTA, INTB outputs to the 3-state mode and OP output to HIGH state logic 1 = forces the INTA-INTB outputs to the active state and OP output to LOW state. In Loopback mode, controls MSR[7]. 2 MCR[2] FIFO Ready enable. logic 0 = disable the FIFO Rdy register logic 1 = enable the FIFO Rdy register. In Loopback mode, controls MSR[6]. 1 MCR[1] RTS logic 0 = force RTS output to inactive (HIGH) logic 1 =force RTS output to active (LOW). In loopback mode, controls MSR[4]. If auto-RTS is enabled, the RTS output is controlled by hardware flow control. 0 MCR[0] DTR logic 0 = force DTR output to inactive (HIGH) logic 1 = force DTR output to active (LOW). In Loopback mode, controls MSR[5]. [1] MCR[7:5] can only be modified when EFR[4] is set, i.e., EFR[4] is a write enable. Symbol MCR[7][1] SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 25 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.7 Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the mode, data set, or peripheral device to the processor. It also indicates when a control input from the modem changes state. Table 15 shows Modem Status Register bit settings per channel. Table 15. Bit 7 6 5 4 Modem Status Register bits description Description CD (active HIGH, logic 1)[1]. This bit is the complement of the CD input during normal mode. During internal Loopback mode, it is equivalent to MCR[3]. RI (active HIGH, logic 1)[1]. This bit is the complement of the RI input during normal mode. During internal Loopback mode, it is equivalent to MCR[2]. DSR (active HIGH, logic 1)[1]. This bit is the complement of the DSR input during normal mode. During Internal Loopback mode, it is equivalent MCR[0]. CTS (active HIGH, logic 1)[1]. This bit is the complement of the CTS input during normal mode. During internal Loopback mode, it is equivalent to MCR[1]. CD. Indicates that CD input (or MCR[3] in Loopback mode) has changed state. Cleared on a read. RI. Indicates that RI input (or MCR[2] in Loopback mode) has changed state from LOW to HIGH. Cleared on a read. DSR. Indicates that DSR input (or MCR[0] in Loopback mode) has changed state. Cleared on a read. CTS. Indicates that CTS input (or MCR[1] in Loopback mode) has changed state. Cleared on a read. Symbol MSR[7] MSR[6] MSR[5] MSR[4] 3 2 1 0 [1] MSR[3] MSR[2] MSR[1] MSR[0] The primary inputs RI, CD, CTS, DSR are all active LOW, but their registered equivalents in the MSR and MCR (in Loopback) registers are active HIGH. SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 26 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.8 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from LOW to HIGH. The INT output signal is activated in response to interrupt generation. Table 16 shows Interrupt Enable Register bit settings. Table 16. Bit 7 Interrupt Enable Register bits description Description CTS interrupt enable. logic 0 = disable the CTS interrupt (normal default condition) logic 1 = enable the CTS interrupt 6 IER[6][1] RTS interrupt enable. logic 0 = disable the RTS interrupt (normal default condition) logic 1 = enable the RTS interrupt 5 IER[5][1] Xoff interrupt. logic 0 = disable the Xoff interrupt (normal default condition) logic 1 = enable the Xoff interrupt 4 IER[4][1] Sleep mode. logic 0 = disable Sleep mode (normal default condition) logic 1 = enable Sleep mode. See Section 6.7 "Sleep mode" for details. 3 IER[3] Modem Status Interrupt. logic 0 = disable the Modem Status Register interrupt (normal default condition) logic 1 = enable the Modem Status Register interrupt 2 IER[2] Receive Line Status interrupt. logic 0 = disable the receiver line status interrupt (normal default condition) logic 1 = enable the receiver line status interrupt 1 IER[1] Transmit Holding Register interrupt. logic 0 = disable the THR interrupt (normal default condition) logic 1 = enable the THR interrupt 0 IER[0] Receive Holding Register interrupt. logic 0 = disable the RHR interrupt (normal default condition) logic 1 = enable the RHR interrupt [1] IER[7:4] can only be modified if EFR[4] is set, i.e., EFR[4] is a write enable. Re-enabling IER[1] will not cause a new interrupt if the THR is below the threshold. Symbol IER[7][1] SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 27 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.9 Interrupt Identification Register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 17 shows Interrupt Identification Register bit settings. Table 17. Bit 7:6 5 4 3:1 0 Interrupt Identification Register bits description Description Mirror the contents of FCR[0] RTS/CTS LOW-to-HIGH change of state 1 = Xoff/Special character has been detected 3-bit encoded interrupt. See Table 18. Interrupt status. logic 0 = an interrupt is pending logic 1 = no interrupt is pending Symbol IIR[7:6] IIR[5] IIR[4] IIR[3:1] IIR[0] The interrupt priority list is shown in Table 18. Table 18. Priority level 1 2 2 3 4 5 6 Interrupt priority list IIR[5] 0 0 0 0 0 0 1 IIR[4] 0 0 0 0 0 1 0 IIR[3] 0 1 0 0 0 0 0 IIR[2] 1 1 1 0 0 0 0 IIR[1] 1 0 0 1 0 0 0 IIR[0] 0 0 0 0 0 0 0 Source of the interrupt Receiver Line Status error Receiver time-out interrupt RHR interrupt THR interrupt Modem interrupt Received Xoff signal/ special character CTS, RTS change of state from active (LOW) to inactive (HIGH) 7.10 Enhanced Feature Register (EFR) This 8-bit register enables or disables the enhanced features of the UART. Table 19 shows the Enhanced Feature Register bit settings. Table 19. Bit 7 Enhanced Feature Register bits description Description CTS flow control enable. logic 0 = CTS flow control is disabled (normal default condition) logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH signal is detected on the CTS pin. 6 EFR[6] RTS flow control enable. logic 0 = RTS flow control is disabled (normal default condition) logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when the receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when the receiver FIFO resume transmission trigger level TCR[7:4] is reached. Symbol EFR[7] SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 28 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Enhanced Feature Register bits description ...continued Description Special character detect. logic 0 = special character detect disabled (normal default condition) logic 1 = special character detect enabled. Received data is compared with Xoff2 data. If a match occurs, the received data is transferred to FIFO and IIR[4] is set to a logic 1 to indicate a special character has been detected. Table 19. Bit 5 Symbol EFR[5] 4 EFR[4] Enhanced functions enable bit. logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4], MCR[7:5] logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] can be modified, i.e., this bit is therefore a write enable. 3:0 EFR[3:0] Combinations of software flow control can be selected by programming these bits. See Table 3 "Software flow control options (EFR[0:3])". 7.11 Divisor latches (DLL, DLM) These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLM stores the most significant part of the divisor. DLL stores the least significant part of the divisor. Note that DLL and DLM can only be written to before Sleep mode is enabled, i.e., before IER[4] is set. 7.12 Transmission Control Register (TCR) This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission during hardware/software flow control. Table 20 shows Transmission Control Register bit settings. Table 20. Bit 7:4 3:0 Transmission Control Register bits description Description RX FIFO trigger level to resume transmission (0 to 60). RX FIFO trigger level to halt transmission (0 to 60). Symbol TCR[7:4] TCR[3:0] TCR trigger levels are available from 0 bytes to 60 bytes with a granularity of four. Remark: TCR can only be written to when EFR[4] = logic 1 and MCR[6] = logic 1. The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware check to make sure this condition is met. Also, the TCR must be programmed with this condition before auto-RTS or software flow control is enabled to avoid spurious operation of the device. SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 29 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.13 Trigger Level Register (TLR) This 8-bit register is pulsed to store the transmit and received FIFO trigger levels used for DMA and interrupt generation. Trigger levels from 4 to 60 can be programmed with a granularity of 4. Table 21 shows trigger level register bit settings. Table 21. Bit 7:4 3:0 Trigger Level Register bits description Description RX FIFO trigger levels (4 to 60), number of characters available TX FIFO trigger levels (4 to 60), number of spaces available Symbol TLR[7:4] TLR[3:0] Remark: TLR can only be written to when EFR[4] = logic 1 and MCR[6] = logic 1. If TLR[3:0] or TLR[7:4] are logic 0, the selectable trigger levels via the FIFO Control Register (FCR) are used for the transmit and receive FIFO trigger levels. Trigger levels from 4 bytes to 60 bytes are available with a granularity of four. The TLR should be programmed for N4, where N is the desired trigger level. When the trigger level setting in TLR is zero, the SC16C752B uses the trigger level setting defined in FCR. If TLR has non-zero trigger level value, the trigger level defined in FCR is discarded. This applies to both transmit FIFO and receive FIFO trigger level setting. When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state, i.e., `00'. 7.14 FIFO ready register The FIFO ready register provides real-time status of the transmit and receive FIFOs of both channels. Table 22. Bit 7:6 5 4 3:2 1 0 FIFO Ready Register bits description Description unused; always 0 RX FIFO B status. Related to DMA. RX FIFO A status. Related to DMA. unused; always 0 TX FIFO B status. Related to DMA. TX FIFO A status. Related to DMA. Symbol FIFO Rdy[7:6] FIFO Rdy[5] FIFO Rdy[4] FIFO Rdy[3:2] FIFO Rdy[1] FIFO Rdy[0] The FIFO Rdy register is a read-only register that can be accessed when any of the two UARTs is selected CSA or CSB = logic 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and loopback is disabled. The address is 111. SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 30 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 8. Programmer's guide The base set of registers that is used during high-speed data transfer have a straightforward access method. The extended function registers require special access bits to be decoded along with the address lines. The following guide will help with programming these registers. Note that the descriptions below are for individual register access. Some streamlining through interleaving can be obtained when programming all the registers. Table 23. Command Set baud rate to VALUE1, VALUE2 Register programming guide Actions Read LCR (03), save in temp Set LCR (03) to 80 Set DLL (00) to VALUE1 SET DLM (01) to VALUE2 Set LCR (03) to temp Set Xoff1, Xon1 to VALUE1, VALUE2 Read LCR (03), save in temp Set LCR (03) to BF Set Xoff1 (06) to VALUE1 SET Xon1 (04) to VALUE2 Set LCR (03) to temp Set Xoff2, Xon2 to VALUE1, VALUE2 Read LCR (03), save in temp Set LCR (03) to BF Set Xoff2 (07) to VALUE1 SET Xon2 (05) to VALUE2 Set LCR (03) to temp Set software flow control mode to VALUE Read LCR (03), save in temp Set LCR (03) to BF Set EFR (02) to VALUE Set LCR (03) to temp Set flow control threshold to VALUE Read LCR (03), save in temp1 Set LCR (03) to BF Read EFR (02), save in temp2 Set EFR (02) to 10 + temp2 Set LCR (03) to 00 Read MCR (04), save in temp3 Set MCR (04) to 40 + temp3 Set TCR (06) to VALUE Set MCR (04) to temp3 Set LCR (03) to BF Set EFR (02) to temp2 Set LCR (03) to temp1 SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 31 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Register programming guide ...continued Actions Read LCR (03), save in temp1 Set LCR (03) to BF Read EFR (02), save in temp2 Set EFR (02) to 10 + temp2 Set LCR (03) to 00 Read MCR (04), save in temp3 Set MCR (04) to 40 + temp3 Set TLR (07) to VALUE Set MCR (04) to temp3 Set LCR (03) to BF Set EFR (02) to temp2 Set LCR (03) to temp1 Table 23. Command Set TX FIFO and RX FIFO thresholds to VALUE Read FIFO Rdy register Read MCR (04), save in temp1 Set temp2 = temp1 x EF[1] Set MCR (04) = 40 + temp2 Read FFR (07), save in temp2 Pass temp2 back to host Set MCR (04) to temp1 Set prescaler value to divide-by-1 Read LCR (03), save in temp1 Set LCR (03) to BF Read EFR (02), save in temp2 Set EFR (02) to 10 + temp2 Set LCR (03) to 00 Read MCR (04), save in temp3 Set MCR (04) to temp3 x 7F[1] Set LCR (03) to BF Set EFR (02) to temp2 Set LCR (03) to temp1 Set prescaler value to divide-by-4 Read LCR (03), save in temp1 Set LCR (03) to BF Read EFR (02), save in temp2 Set EFR (02) to 10 + temp2 Set LCR (03) to 00 Read MCR (04), save in temp3 Set MCR (04) to temp3 + 80 Set LCR (03) to BF Set EFR (02) to temp2 Set LCR (03) to temp1 [1] x sign here means bit-AND. SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 32 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 9. Limiting values Table 24. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC Vn Tamb Tstg Parameter supply voltage voltage on any other pin ambient temperature storage temperature at D7 to D0 pins at any input only pin operating in free-air Conditions Min GND - 0.3 GND - 0.3 -40 -65 Max 7 VCC + 0.3 5.3 +85 +150 Unit V V V C C 10. Static characteristics Table 25. Static characteristics VCC = 2.5 V, 3.3 V 10 % or 5 V 10 %. Symbol Parameter VCC VI VIH VIL VO VOH supply voltage input voltage HIGH-level input voltage LOW-level input voltage output voltage HIGH-level output voltage IOH = -8 mA IOH = -4 mA IOH = -800 A IOH = -400 A VOL LOW-level output IOL = 8 mA voltage[5] IOL = 4 mA IOL = 2 mA IOL = 1.6 mA Ci Tamb Tj ICC input capacitance ambient temperature junction temperature clock duty cycle supply current f = 5 MHz [7] [8] [1] Conditions Min VCC = 2.5 V Typ VCC 25 25 50 Max VCC VCC 0.65 VCC 0.4 0.4 18 85 125 3.5 50 VCC - 10 % 0 1.6 0 1.85 1.85 -40 [6] VCC = 3.3 V or 5 V Min 0 2.0 0 2.0 2.0 -40 0 Typ VCC 25 25 50 Max Unit VCC + 10 % VCC - 10 % VCC + 10 % V VCC VCC 0.8 VCC 0.4 0.4 18 85 125 4.5 50 V V V V V V V V V V V V pF C C % mA A [1] [2] [3] [4] [3] [4] [3] [4] [3] [4] operating 0 - ICC(sleep) sleep mode supply current [1] [2] [3] [4] Meets TTL levels, VIO(min) = 2 V and VIH(max) = 0.8 V on non-hysteresis inputs. Applies for external output buffers. These parameters apply for D7 to D0. These parameters apply for DTRA, DTRB, INTA, INTB, RTSA, RTSB, RXRDYA, RXRDYB, TXRDYA, TXRDYB, TXA, TXB. (c) NXP B.V. 2008. All rights reserved. SC16C752B_5 Product data sheet Rev. 05 -- 2 October 2008 33 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs [5] [6] [7] Except XTAL2, VOL = 1 V typical. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150 C. The customer is responsible for verifying junction temperature. Measurement condition, normal operation other than Sleep mode: VCC = 3.3 V; Tamb = 25 C. Full duplex serial activity on all two serial (UART) channels at the clock frequency specified in the recommended operating conditions with divisor of 1. Sleep mode current might be higher if there is activity on the UART data bus during Sleep mode. [8] 11. Dynamic characteristics Table 26. Dynamic characteristics Tamb = -40 C to +85 C; VCC = 2.5 V, 3.3 V 10 % or 5 V 10 %, unless specified otherwise. Symbol td1 td2 td3 td4 td5 td6 td7 td8 td9 td10 td11 td12 td13 td14 td15 td16 td17 td18 td19 th1 th2 th3 th4 th5 tp1 tp2 fXTAL1 tw(RESET) tsu1 SC16C752B_5 Parameter IOR delay from chip select read cycle delay delay from IOR to data data disable time IOW delay from chip select write cycle delay delay from IOW to output delay to set interrupt from modem input delay to reset interrupt from IOR delay from stop to set interrupt delay from IOR to reset interrupt delay from start to set interrupt delay from IOW to transmit start delay from IOW to reset interrupt delay from stop to set RXRDY delay from IOR to reset RXRDY delay from IOW to set TXRDY delay from start to reset TXRDY delay between successive assertion of IOW and IOR chip select hold time from IOR chip select hold time from IOW data hold time address hold time hold time from XTAL1 clock HIGH-to-LOW transition to IOW or IOR release clock cycle period clock cycle period frequency on pin XTAL1 pulse width on pin RESET address set-up time Conditions VCC = 2.5 V Min 10 Max 77 15 100 100 100 1TRCLK[1] 100 100 24TRCLK[1] 100 1TRCLK[1] 100 100 16TRCLK 20 48 [1] VCC = 3.3 V or 5 V Unit Min 0 20 10 25 8 0 0 15 0 20 6 6 40 0 Max 26 15 33 24 24 1TRCLK[1] 29 100 70 1TRCLK 75 70 16TRCLK[1] 20 80 [1] ns ns ns ns ns ns ns ns ns s ns ns ns s ns ns s ns ns ns ns ns ns ns ns MHz ns ns 25 pF load 25 pF load 25 pF load 20 10 25 25 pF load 25 pF load 25 pF load 25 pF load 8 0 0 15 0 20 10 10 [2] [3] 24TRCLK[1] s 100 0 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 34 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Table 26. Dynamic characteristics ...continued Tamb = -40 C to +85 C; VCC = 2.5 V, 3.3 V 10 % or 5 V 10 %, unless specified otherwise. Symbol tsu2 tsu3 tw1 tw2 [1] [2] [3] Parameter data set-up time set-up time from IOW or IOR assertion to XTAL1 clock LOW-to-HIGH transition IOR strobe width IOW strobe width Conditions VCC = 2.5 V Min 16 20 77 30 Max - VCC = 3.3 V or 5 V Unit Min 16 20 30 30 Max ns ns ns ns RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches. Applies to external clock; crystal oscillator max 24 MHz. Reset pulse must happen when CSA, CSB, IOR, IOW are inactive. 11.1 Timing diagrams A0 to A2 tsu1 valid address th4 CSA, CSB td1 active th1 tw1 active td3 td2 IOR td4 D0 to D7 data 002aaa235 Fig 14. General read timing SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 35 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs A0 to A2 tsu1 valid address th4 CSA, CSB td5 active th2 tw2 active tsu2 td6 IOW th3 D0 to D7 data 002aaa236 Fig 15. General write timing IOW active td7 RTSA, RTSB DTRA, DTRB change of state change of state CDA, CDB CTSA, CTSB DSRA, DSRB td8 change of state td8 change of state INTA, INTB active td9 active active IOR active active td8 active RIA, RIB change of state 002aaa238 Fig 16. Modem input/output timing SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 36 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Start bit data bits (0 to 7) D0 D1 D2 5 data bits 6 data bits 7 data bits D3 D4 D5 D6 D7 parity bit Stop bit next data Start bit RXA, RXB td10 active td11 active INTA, INTB IOR 16 baud rate clock 002aaa239 Fig 17. Receive timing start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit next data start bit RXA, RXB td15 RXRDYA RXRDYB active data ready td16 IOR active 002aab240 Fig 18. Receive ready timing in non-FIFO mode SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 37 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit RXA, RXB first byte that reaches the trigger level td15 RXRDYA RXRDYB active data ready td16 IOR active 002aaa241 Fig 19. Receive ready timing in FIFO mode Start bit data bits (0 to 7) D0 D1 D2 5 data bits 6 data bits 7 data bits D3 D4 D5 D6 D7 parity bit Stop bit next data Start bit TXA, TXB td12 INTA, INTB td13 active active TX ready td14 active IOW 16 baud rate clock 002aaa242 Fig 20. Transmit timing SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 38 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit next data start bit TXA, TXB IOW active D0 to D7 byte #1 td18 td17 TXRDYA TXRDYB active transmitter ready transmitter not ready 002aaa243 Fig 21. Transmit ready timing in non-FIFO mode start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit TXA, TXB 5 data bits 6 data bits 7 data bits IOW active td18 D0 to D7 byte #64 td17 TXRDYA TXRDYB trigger lead 002aaa244 Fig 22. Transmit ready timing in FIFO mode SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 39 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 37 25 24 ZE A e E HE A A2 A1 (A 3) Lp L detail X wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 23. Package outline SOT313-2 (LQFP48) SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 40 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm SOT617-1 D B A terminal 1 index area E A A1 c detail X e1 e 9 L 8 17 e 1/2 e C b 16 vMCAB wMC y1 C y Eh 1/2 e e2 1 terminal 1 index area 24 32 Dh 0 2.5 scale E (1) 5.1 4.9 Eh 3.25 2.95 e 0.5 e1 3.5 e2 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm 25 X DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 5.1 4.9 Dh 3.25 2.95 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT617-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18 Fig 24. Package outline SOT617-1 (HVQFN32) SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 41 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 42 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 13.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 25) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 27 and 28 Table 27. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 28. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 25. SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 43 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". 14. Abbreviations Table 29. Acronym CPU DMA FIFO TTL UART Abbreviations Description Central Processing Unit Direct Memory Access First In, First Out Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 44 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 15. Revision history Table 30. Revision history Release date 20081002 Data sheet status Product data sheet Change notice Supersedes SC16C752B_4 Document ID SC16C752B_5 Modifications: * * * * * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 2 "Features", 10th bullet item re-written; added Footnote 1 on page 2 Section 7.5 "Line Status Register (LSR)": deleted "Remark" following 3rd paragraph after Table 13 Table 24 "Limiting values": - deleted symbol VO - deleted symbol VI - added symbol Vn (split to show 2 separate conditions: "at D7 to D0 pins" and "at input only pins") * SC16C752B_4 SC16C752B-03 (9397 750 14443) Modifications: Table 25 "Static characteristics", Table note [5]: changed "x2" to "XTAL2" Product data sheet Product data SC16C752B-03 SC16C752B-02 20060714 20041214 * There is no modification to the data sheet. However, reader is advised to refer to AN10333 (Rev. 02) "SC16CXXXB baud rate deviation tolerance" (9397 750 14411) that was released together with this revision. Product data Product data SC16C752B-01 - SC16C752B-02 (9397 750 13337) SC16C752B-01 (9397 750 11981) 20040527 20040326 SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 45 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com SC16C752B_5 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 -- 2 October 2008 46 of 47 NXP Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 18. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.3 6.3.1 6.3.2 6.3.3 6.3.3.1 6.4 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.1.1 6.6.1.2 6.6.2 6.6.2.1 6.6.2.2 6.7 6.8 6.9 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 Trigger levels. . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Hardware flow control . . . . . . . . . . . . . . . . . . . . 7 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Software flow control . . . . . . . . . . . . . . . . . . . . 9 RX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Software flow control example . . . . . . . . . . . . 11 Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Interrupt mode operation . . . . . . . . . . . . . . . . 14 Polled mode operation . . . . . . . . . . . . . . . . . . 14 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 15 Single DMA transfers (DMA mode 0/FIFO disable). . . . . . . . . . . . . . 15 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block DMA transfers (DMA mode 1). . . . . . . . 16 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Break and time-out conditions . . . . . . . . . . . . 17 Programmable baud rate generator . . . . . . . . 17 Register descriptions . . . . . . . . . . . . . . . . . . . 19 Receiver Holding Register (RHR). . . . . . . . . . 21 Transmit Holding Register (THR) . . . . . . . . . . 21 FIFO Control Register (FCR) . . . . . . . . . . . . . 22 Line Control Register (LCR) . . . . . . . . . . . . . . 23 Line Status Register (LSR) . . . . . . . . . . . . . . . 24 Modem Control Register (MCR) . . . . . . . . . . . 25 Modem Status Register (MSR). . . . . . . . . . . . 26 Interrupt Enable Register (IER) . . . . . . . . . . . 27 Interrupt Identification Register (IIR). . . . . . . . 28 Enhanced Feature Register (EFR) . . . . . . . . . 28 Divisor latches (DLL, DLM). . . . . . . . . . . . . . . 29 Transmission Control Register (TCR) . . . . . . . 29 Trigger Level Register (TLR). . . . . . . . . . . . . . 30 FIFO ready register. . . . . . . . . . . . . . . . . . . . . 30 8 9 10 11 11.1 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 Programmer's guide . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 33 33 34 35 40 42 42 42 42 43 44 45 46 46 46 46 46 46 47 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 October 2008 Document identifier: SC16C752B_5 |
Price & Availability of SC16C752BIB48
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